1. Field of the Invention
The present invention generally relates to electronic design automation, and more particularly to a method of macro placement.
2. Description of Related Art
Electronic design automation (EDA) is a tool for designing an integrated circuit. Chip designers use the EDA tool to design and analyze a semiconductor chip. Placement is an essential step in EDA to assign locations for various circuit components such as macros within chip area. To ensure performance demands, a placer must optimize some criteria such as total wirelength, timing, congestion, power and placement runtime.
Conventional EDA placement methods cannot efficiently handle floating preplaced macros that are not abutted to a chip outline or cannot connect to a chip outline through preplaced macros. Further, the conventional EDA placement methods are not capable of handling a large number of (e.g., more than ten) macros. Macro placement problem becomes worse when there exist many preplaced macros and/or floating preplaced macros.
For the reasons that conventional EDA placement methods cannot perform effectively, a need has arisen to propose a novel macro legalizer that can efficiently handle floating preplaced macros and large number of preplaced macros.